Crosspoint Switch FPGA
(OPTICAL STANDARDS TEST EQUIPMENT)

OTN/SONET/10GbE/POS Crosspoint Switch FPGA

This Xilinx Virtex2 XC2V6000 architecture enabled full-duplex communications between a Pattern Generation and BERT Analysis FPGA (see “OPTICAL COMMUNICATIONS FPGA” below), an AMCC Khatanga SONET Framer, and an AMCC Hudson Digital Wrapper and FEC device. The 16-bit LVDS interface to the framer devices and 64-bit HSTL interface to the FPGA were designed to operate at 622M/644/669Mhz to satisfy SONET (9.95 Gbps), 10GbE LAN (10.304 Gbps), and Optical Transport Network (OTN) (10.709 Gbps) requirements. The complexity and performance of this design required special attention to clock resource management featuring Xilinx DCMs (Digital Clock Manager), as well as floorplanning techniques and module location assignments to achieve the desired post-route timing. Each port included an internal data pattern generator (e.g. PRBS 231 and custom patterns) and monitor for evaluating link integrity and isolation diagnostics.

EDA tools: VHDL entry, Leonardo Spectrum for synthesis, Modelsim PE for simulation, and Xilinx Project Navigator for place&route.

SONET/10GbE/POS Pattern Generation and BERT Analysis FPGA

This PCI-based Xilinx Virtex2 XC2V6000 design contained a transmitter for generating an assortment of data patterns (PRBS patterns, custom RAM-based patterns, and 10GbE/POS packets with IPv4 encapsulation, address ramping, MPLS labeling) and a receiver for monitoring traffic. The receiver checked and accumulated bit error rate (BER) statistics, verified 10GbE/POS/IP/PPP protocol, parsed header fields for packet statistics, and captured data through an external Dual Data Rate (DDR) SRAM. The generated traffic was transmitted to two framers in parallel: AMCC Khatanga SONET Framer through a 64-bit, 180 Mhz Flexbus4 (SPI4) interface, and an AMCC Hudson Digital Wrapper Framer through a crosspoint switch FPGA (see “CROSSPOINT SWITCH FPGA” project above). This design also included a 1GbE frame generator and monitor, along with direct control of physical layer system components such as lasers and attenuators.

EDA tools: VHDL entry, Leonardo Spectrum for synthesis, Modelsim PE for simulation, and Xilinx Project Navigator for place&route.

Simulation Environment for Board-level Verification of Optical Test System

This VHDL/Verilog simulation environment for ModelSim PE simulator was used to verify two Xilinx XC2V6000 FPGA designs (see “Crosspoint Switch FPGA” and “Optical Communications FPGA” above) along with other board-level components within an optical standards test system. Included within this environment were models of the AMCC Khatanga SONET/10GbE Framer, the AMCC Hudson Digital Wrapper/FEC Framer, a PCI initiator, and Dual Data Rate (DDR) SRAM. Simulation was executed in either operating system batch files for background execution or ModelSim GUI batch files for troubleshooting. A suite of tests and configurations was required in order to verify all Bit mode (PRBS and other data patterns) and Packet mode (10GbE/POS/IP/1GbE) processing.

Dual-channel OC3/OC12 Packet-over-SONET (POS) Network Monitoring FPGA.

This architecture included custom Rx and Tx POS-PHY interface modules that directly interfaced to the AMCC Congo S1201 PHY device. The design included an integrated Xilinx PCI 64-bit/66 MHz Initiator/target Core for PCI bus access. The target FPGA was the Xilinx Virtex XCV300E in a BG432 package. EDA tools included Exemplar Logic Leonardo Spectrum for synthesis and Model Technology ModelSIM PE for simulation. Simulation environment was based on mixed VHDL/Verilog models including the PHY device, a PCI target, and a PCI initiator. The test suite included verification of special PCI conditions such as target disconnect, target retry, target initial latency/wait states, and target abort.

HMVIP-based Multiport Timeslot Interchange FPGA.

This VHDL-based design provided a timeslot interchange (in real time) for 16 full-duplex ports. Each TDM-based port is comprised of 128-timeslots, at a bandwidth of 64kbps per timeslot. The architecture supported the Multi-Vendor Integration Protocol (H-MVIP) along with the serial multi-channel controller (MCC) interface of the MPC8260 communications microprocessor. The target FPGA was the Xilinx Virtex XCV400E in a FG676 package. EDA tools included Exemplar Logic Leonardo Spectrum for synthesis and Model Technology ModelSIM PE for simulation.

Full duplex interface module used for transferring encapsulated MPEG packets between a 2.125 Gbps Vitesse chipset based crosspoint switching system and a 1.25 Gbps local proprietary network.

Architecture included virtual output queue (VOQ) DPRAM configuration, multi-queue timing with early arbitration for sending packets to the Vitesse VSC870 transceiver, external FIFO interface for retrieving packets from the VSC870, a CAM route table lookup, an independent ping messaging controller, and CRC generation/checking. Several embedded dual-clock buffers were used for transferring packets between the multiple clock domains. Verification included a multiboard environment used for transferring test packets through the Vitesse VSC880 switch model. Source code language was Verilog HDL. Target device was the Altera 10K200E in a 672-pin package.

Verilog-based controller design that coordinated the transfer of up to 768 unique packet streams upon request from an external rate controller.

The status and configuration of each packet stream, such as destination address and memory pointers, was maintained in hardware descriptor blocks stored in external synchronous SRAM. An internal 4-way memory controller handled accesses from multiple nodes using a single data and address bus. The architecture contained several independent sequencer units that performed a unique function for each stream transfer request. The target performance was 66 MHz using Altera 10K200E technology.

Verilog-based controller FPGA used for synchronizing the transfer of up to 768 packet streams based on a direct digital frequency synthesis implementation.

Architecture included six parallel processor units each composed of embedded RAM and 32-bit accumulators for frequency synthesis function. Two clock domains were used: 66 MHz for the system interface and 62.5 MHz core rate generation logic. Target device was the Altera 10K130E FPGA.

Dual FPGA implementation of a PCI-based network interface controller which performed frame-building and buffering for 32 generic communication links, each sharing a common proprietary bus interface.

The VHDL-based design targeted two Lucent ORCA FPGAs (3T80 and 2T40), utilizing several embedded RAM structures and an external DPRAM. A PCI master-target IP core was adapted to provide 33 MHz 0WS frame bursts from local DRAM to the PCI bus. The design was used within an embedded PowerPC MPC860-based system.

Combination FPGA/CPLD design of an IP-over-ATM packet forwarding engine targeting 540 Mbps performance.

The VHDL-based design was synthesized using Synopsys FPGA Express and verified using Model Technology simulator. The verification environment included models for external DPRAMs, a SAR device, and peripheral custom interfaces. The design was partitioned over two programmable parts: the Altera 10K50 FPGA and the Altera 7192 CPLD.

ASIC design of an MPEG/AC-3 Audio Decoder core.

The Verilog-based design was synthesized using Synopsys Design Compiler and verified using Viewlogic VCS and Mentor QuickHDL simulator. Synthesis scripts included a mixture of optimization strategies such as top-down and characterize-write script-recompile.

PCMCIA Card used for interfacing an ATM LAN Adapter Module to a mobile computer within a Broadband Services Network.

The PC Card bus controller was programmed within an Altera 8452 FPGA in a 100-pin TQFP package. The next generation design incorporated wireless Internet access capability based on a 3.3V Orca 2T15 FPGA and two IDT 72V255 SuperSYNC FIFOs used for transmit and receive buffers.

VME-based, 32 channel data acquisition PCB used for the digitization and processing of analog photomultiplier tube (PMT) signals in a Positron Emission Tomography (PET) Scanner.

This design featured 8-bit flash ADCs and low-skew clock distribution using Motorola 88915 PLL devices. An array of Xilinx 4005 FPGAs was used for performing dual accumulator and FIFO functions on each channel. Also designed a next-generation, 48-channel version using Xilinx 5210 FPGAs.

VME-based global synchronization PCB used for providing a high-stability master timebase in a TDMA-based Multimedia Network application.

This design featured a four-level interrupt control scheme, a temperature-controlled crystal oscillator (TCXO), and loopback self-test capability. An Altera 8452 FPGA was used to perform programmable Timebase Modulus functions.

VME-based, real-time back-projection volume imaging design for a Positron Emission Tomography (PET) Scanner.

This 9Ux400mm PCB design was performance-driven and featured three separate DRAM modules and four independent sequencers operating in a dataflow pipeline architecture. An array of Xilinx 4005 FPGAs was used as Bank Processing Elements, each with local DRAM memory in a parallel-processing configuration. Altera EPLDs and Xilinx 4003 FPGAs were used for assorted sequencer and arithmetic operations.