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Design
Entry
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- Esprimo Visual SlickEdit HDL
- Premia Sledgehammer/Codewrite HDL
- Cadence Concept Schematic Capture
- OrCAD Schematic Capture
- CUPL, PALASM, ABEL
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Simulation
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- Model Technology V-System VHDL
- SimuCAD Silos III Verilog
- Mentor QuickHDL Verilog
- Viewlogic
VCS & ViewSIM
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Synthesis
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- Exemplar Logic Leonardo Spectrum
- Synopsys FPGA Express
- Synopsys ASIC Design Compiler
- Synplicity Synplif
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Place & Route
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- Altera Maxplus II
- Lucent ORCA Foundry
- Viewlogic ViewPLD
- Xilinx Foundation Series
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Miscellaneous
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- Chronology TimingDesigner
- VISIO Drawing
- Cadence Allegro PCB Design
- Viewlogic ViewPLD
- Xilinx XACT Design Manager
- C, Fortran, Assembly (680x0, 80x86)
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