Optimal Design, Inc.

Optimal Design specializes in large-scale digital design targeting
FPGAs, ASICs, and IP cores.

John Cappello, lead consultant for Optimal Design, specializes in large-scale digital design targeting FPGAs, ASICs, and IP cores. Refer to his PDF Profile for a project listing of his experience and the About page for bio and contact info.

For a flavor of the specifications he generates to support the description of his designs, check out the Documentation page.

Expertise in Digital Hardware Design Engineering

FPGA, ASIC, and CPLD • Xilinx and Altera • VHDL and Verilog HDL •
Intellectual Property (IP) Core • Verification through Simulation •
Computer Architecture Optimization • Worst Case Timing Analysis •
System and Board-level Troubleshooting • Project Management and Documentation

EDA Tool & Programming Experience

Esprimo Visual HDL Editor • Mentor ModelSim Simulator •
Synplicity Synplify • Mentor Precision & Leonardo Spectrum •
Synopsys DC Compiler (for ASICs) • Synopsys FPGA Express •
Xilinx ISE/Foundation • Altera Quartus II, MaxPlus II •
EMA TimingDesigner • Visio diagramming • Tcl/Fortran/Assembly/C

Clients

Circadiant Systems • Cyberpath • DIVA • Federal Aviation Administration •
General Instrument • IBM • Inrange Technologies • JDS Uniphase •
Judson Technologies • Lucent • Motorola • Nearfield Systems • Netquest •
Sarnoff • Smiths Industries Aerospace • SpectraSonics Imaging •
UGM Medical Systems • Xilinx

Contact Information

John D. Cappello

856-582-4838 • Fax (856) 582-4885